1. Technical Field
The present invention relates generally to interface signaling, and more particularly, to an interface between a system controller integrated circuit and a plurality of peripheral integrated circuits.
2. Description of the Related Art
Interfaces between present-day integrated circuits have increased in density and variety. In particular, computer systems peripheral components have interfaces that differ based upon the type of peripheral, and all of the peripheral components may have many connections.
Typically, the width of an address and data bus for interconnecting peripheral components to a system controller is determined by the maximum number of address signals and the maximum number of data signals. The width of a control bus may depend upon the variety of control mechanisms used to interface the various peripheral integrated circuits. For example, a memory device may require a read/write line and a strobe line, while an Input/Output (I/O) controller may require a read strobe and a write strobe. Therefore, the total number of interface signals for connection to a group of peripheral devices generally reaches the maximum data and address set plus a variety of control signals that includes all of the required “flavors”, plus a plurality of chip select signals for selecting between the particular peripheral integrated circuits.
Since the above signals have different setup and timing requirements, it is not practical for the logic that generates these signals to shift functions between the functions required for the various peripherals, for example, a memory IC requiring 16 address lines sets a minimum number of address lines in a typical interface to 16. A secondary connection of a bus controller that requires only 5 address lines leaves 11 of the address lines provided on the interface unused for the purposes of interfacing the bus controller. Further for example, if the bus controller requires 6 high-speed control lines and the memory IC requires only 2, but of completely differing types, 8 control signal lines must be provided on the interface. The above design yields 13 unused signal lines during interfaces to the bus controller and 6 unused control lines during interfaces to the memory.
It is therefore desirable to provide a method and apparatus for sharing pins between disparate signals on an interface to a plurality of peripheral integrated circuits.